1. Field of the Invention
The present invention relates to a digital signal processor and, more particularly, to a digital signal processor with a byte direct memory access (DMA) controller.
2. Description of the Related Art
In a digital signal processor system employing static random access memories (SRAMs) as internal memories, in order for the digital signal processor either to execute a certain program immediately after the system is booted or to perform background loading/saving operations during program execution, the most commonly used procedure is as follows. At first, the certain program to be executed immediately after the system is booted is stored in a byte memory installed outside the digital signal processor, such as a read only memory or flash memory. Subsequently, a byte DMA controller installed inside the digital signal processor downloads the certain program from the external byte memory into the SRAM type internal memories for being executed therein.
FIG. 1 is a circuit block diagram showing a conventional digital signal processor. Referring to FIG. 1, the conventional digital signal processor 10 includes a byte DMA controller 11 and an external memory controller 12. Through a dedicated data bus 13, the byte DMA controller 11 directly accesses a byte memory 14. On the other hand, the external memory controller 12 accesses external memories 16 and 17 through another data bus 15.
As can be clearly seen from FIG. 1, the conventional digital signal processor 10 must employ two different data buses 13 and 15 for the byte DMA controller 11 and the external memory controller 12 in order to access the byte memory 14 and the external memories 16 and 17, respectively. Therefore, the conventional digital signal processor 12 needs to be provided with a number of connecting terminals for coupling with the data buses 13 and 15, resulting in a restriction on the size reduction of the conventional digital signal processor 10.
In view of the above-mentioned problem, an object of the present invention is to provide a digital signal processor with a byte DMA controller capable of accessing a byte memory and an external memory through a common data bus, thereby reducing a necessary number of connecting terminals of the digital signal processor.
According to one aspect of the present invention, a digital signal processor is provided for coupling with a byte memory and an external memory through a common data bus, including an internal memory, an external memory controller, a byte DMA controller, and a steal request priority scheduler. In the internal memory is stored at least one word, each of which consists of a plurality of bytes. The external memory controller is coupled with the common data bus. The byte DMA controller is coupled with the external memory controller and includes: a byte DMA steal request circuit for outputting a write steal request; a data buffer coupled with the internal memory for receiving in format of a word the at least one word stored in the internal memory during an execution of the write steal request; a byte DMA request circuit for outputting a write request into the external memory controller after the data buffer has received the at least one word stored in the internal memory; and a byte DMA waiting circuit for periodically outputting a waiting end signal into the external memory controller. The steal request priority scheduler receives the write steal request and makes a schedule for the execution of the write steal request. The external memory controller makes a schedule for an execution of the write request. During the execution of the write request, the external memory controller in response to the waiting end signal transfers in format of a byte the at least one word from the data buffer through the common data bus into the byte memory.
According to another aspect of the present invention, a digital signal processor is provided for coupling with a byte memory and an external memory through a common data bus. In the byte memory is stored at least one word, each of which consists of a plurality of bytes. The digital signal processor includes an external memory controller, a byte DMA controller, a steal request priority scheduler, and an internal memory. The external memory controller is coupled with the common data bus. The byte DMA controller is coupled with the external memory controller and includes: a byte DMA request circuit for outputting a read request into the external memory controller; a byte DMA waiting circuit for periodically outputting a waiting end signal into the external memory controller; a data buffer for receiving the at least one word stored in the byte memory during an execution of the read request; and a byte DMA steal request circuit for outputting a read steal request after the data buffer has received the at least one word stored in the byte memory. The steal request priority scheduler receives the read steal request, makes a schedule for an execution of the read steal request, and outputs a steal acknowledgement into the external memory controller during the execution of the read steal request. The internal memory is coupled with the data buffer for receiving in format of a word the at least one word stored in the data buffer during the execution of the read steal request. The external memory controller makes a schedule for the execution of the read request. During the execution of the read request, the external memory controller in response to the waiting end signal transfers in format of a byte the at least one word from the byte memory through the common data bus into the data buffer.
The digital signal processor according to the present invention allows the byte DMA controller to perform byte DMA operations to the byte memory through the common data bus by controlling the external memory controller, resulting in less connecting terminals than the conventional digital signal processor, thereby achieving a size reduction.